Design of Analog Readout Circuitry with Front-end Multiplexing for Column Parallel Image Sensors

for Column Parallel Image Sensors Steven Huang, David Estrada, Daniel Van Blerkom and Barmak Mansoorian Forza Silicon Corporation, 2947 Bradley Street, Suite 130, Pasadena, CA 91107, USA tel: 626-796-1182, email: [email protected] Abstract This paper reports progress in our column parallel analog signal chain design strategy, utilizing varying degrees of parallelism for CMOS image sensors. In [1] we investigated the trade-offs for different choices of parallelism and presented an analytical model for optimization of an endoscopic sensor. We continue to use the analytical model and have developed an improved analog readout circuitry that has enabled us to reduced silicon area, achieve higher frame rates, while improving SNR performance. The design is highly scalable and has been implemented in both a high-resolution large format sensor at 60FPS and a lower-resolution small form factor sensor at 600FPS. It features a fully differential readout with a high-speed redundant successive approximation A/D converter (SAR-ADC). The analog readout circuitry presented here was tested in a prototype sensor fabricated in 0.18um 3.3V/1.8V CMOS process. The measured results from the prototype sensor shows the signal chain achieving 248uV input referred noise with a throughput of 17.5Mpixel/sec while consuming an estimated 126uW per pixel column. Introduction Design of analog readout circuitry for CMOS image sensors continues to face challenges in achieving high speed, small area, low power, and low noise. We are faced with continual shrinkage of pixel size with increasing requirements on resolution and frame rate. Recent trends for achieving high dynamic range images with multiple high/low exposures reads is also pushing the effective readout rates higher even when the sensor’s effective frame rate remains the same. Confronted with these design parameters of competing criteria, we continue to rely on our analytical model to optimize the degree of parallelism in our analog readout circuit. In this paper, we present an improved analog readout circuit [1] designed in combination with our analytical model to find the optimal degree of parallelism. The improved design is fully differential with a high-speed Successive Approximation (SAR) ADC. The design increases the achievable SNR while reducing supply voltage requirement thus lowering the overall power consumption.